Field of the Disclosure
This document relates to a display device and a method of initializing the gate shift register of the same.
Discussion of the Related Art
In recent years, various types of flat panel displays FPDs have been developed and commercialized. In general, a scan driving circuit of a flat panel display sequentially supplies a scan pulse to scan lines by using a gate shift register.
The gate shift register of the scan driving circuit comprises a plurality of stages each including a plurality of thin film transistors (TFTs). The stages are cascade-connected to one another and sequentially generate output.
Each of the stages includes a Q node for controlling a pull-up transistor and a Q bar (QB) node for controlling a pull-down transistor. Further, each of the stages includes a plurality of switching circuits for controlling the potential of the Q node and the potential of the QB node in response to a start pulse and a shift clock.
In the k-th (k is a positive integer) stage, a shift clock with a particular phase is input through the pull-up TFT while the potential of the Q node is set to the turn-on level and the potential of the QB node is set to the turn-off level, the shift clock with the particular phase is output as a scan pulse for the k-th stage. This scan pulse is supplied to a scan line connected to the k-th stage and at the same time applied as a start pulse for the (k+1)th stage.
The output ends of the stages are connected one to one to the scan lines. A scan pulse output from each stage is generated once every frame and supplied to the corresponding scan line. To this end, the Q node potential of each stage, initialized to the turn-off level, must be set to the turn-on level prior to the timing of scan pulse output and reset to the turn-off level in synchronization with the timing of completion of scan pulse output. On the other hand, the QB node potential of each stage, initialized to the turn-on level, must be set to the turn-off level prior to the timing of scan pulse output and reset to the turn-on level in synchronization with the timing of completion of scan pulse output.
However, the potentials of the Q node and QB node in each of the stages may not be reset properly due to various factors including parasitic capacitance. This occurs when the display device is intermittently driven at long time intervals, especially on a large-area, high-resolution panel carrying a large load current.
When driving power is applied while the potentials of the Q node and QB node are not reset properly, the pull-up TFTs for different stages are simultaneously turned on for several frames during the initial stage of driving to trigger multiple outputs by which multiple scan pulses are output. Multiple outputs degrade display quality. Moreover, when multiple pull-up TFTs are simultaneously turned on, this may cause over-current and paralyze the operation of a module power supply within the display device.